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TI Pro-Clock?
disable output
Choose which outputs will be disabled. The Switch A will be set to input clock and P
Divider will be set to 1 for each disabled output.
An Error is displayed, if the setup cannot be provided by the CDCE906/CDCE706
A Warning is displayed if something in the setup needs special attention from the user.
The Accept Setup button transfers the setup to the CDCE906-706 SMBus interface , where an individual
adjustment of the setup is possible. This function is blocked if an error in the setup occurs. Discard Setup
returns to the SMBus Interface without transferring the setup.
4.3
Tutorial
This section contains a step-by-step tutorial for creating a user-defined setup and programming the
CDCE906/E706. The 27-MHz crystal of the EVM is used for reference. A 64-MHz CPU clock, different
audio sample clocks for 24-kHz audio rate, a 27-MHz clock for an MPEG/AC-3 Audio Dec, and an
additional 60-MHz clock is provided. The tutorial contains instructions and comments explaining the
functionality of the software.
Step-by-step instruction:
1. Start TI Pro-Clock?.
2. Select CDCE906/E706.
?
The CDCE906-706 SMBus Interface is started.
3. Select Programming Assistant in the menu bar.
?
The CDCE906-706 Programming Assistant is started.
4. Select CDCE906 Default Setting from Default Setup in the menu bar.
?
All Outputs are in use. All PLLs are in bypass mode.
5. Click disable output for Y1-Y5.
?
Only Y0 is in use. All PLLs are in bypass mode.
6. Set fout of Y0 to 64 MHz.
?
Y0 has an output frequency of 64 MHz; PLL 1 is set up automatically.
7. Click disable output for Y1.
8. Set fout of Y1 to 9.216 MHz.
?
Y1 is set to 9.216 MHz; PLL 2 in use by Y1.
9. Click disable output for Y2.
10. Set fout of Y2 to 18.432 MHz.
?
18.432 MHz is set to Y2; PLL 1 is in use by Y1 and Y2 because Y1 and Y2 are derived from the
same PLL (groups of outputs are preferred to a single output).
11. Click disable output for Y3.
12. Set fout of Y3 to 6.144 MHz.
?
Y1, Y2, and Y3 are derived by PLL 1.
13. Click disable output for Y4.
14. Set fout of Y4 to 27 MHz.
?
27 MHz is provided to Y4 by the input clock; PLL 3 is still not in use.
The 27 MHz of Y4 can be provided by a PLL if additional jitter cleaning is necessary:
1. Click disable PLL bypass at Y4.
?
PLL3 now provides 27 MHz; additional jitter cleaning is possible.
2. Click disable output at Y5.
3. Set fout of Y5 to 60 MHz.
?
Error message The error for fout of Y5 is not procurable! appears; this is why no PLL is left to
12
CDCE906/CDCE706 Programming Evaluation Module
SCAU017B – August 2006 – Revised August 2007
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相关代理商/技术参数
CDCE906-706ProgEVM 功能描述:时钟和定时器开发工具 HEADPHONE DRIVER RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V
CDCE906PW 功能描述:时钟合成器/抖动清除器 Programmable 3-PLL Clock Synth/Mul/Dvdr RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel
CDCE906PW 制造商:Texas Instruments 功能描述:CLOCK DRIVER 制造商:Texas Instruments 功能描述:IC PLL CLOCK SYNTHESIZER 167MHZ TSSOP-20
CDCE906PWG4 功能描述:时钟合成器/抖动清除器 Programmable 3-PLL Clock Synth/Mul/Dvdr RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel
CDCE906PWR 功能描述:时钟合成器/抖动清除器 Programmable 3-PLL Clock Synth/Mul/Dvdr RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel
CDCE906PWRG4 功能描述:时钟合成器/抖动清除器 Programmable 3-PLL Clock Synth/Mul/Dvdr RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel
CDCE906R005PWR 制造商:Texas Instruments 功能描述:
CDCE906R007PWR 制造商:Texas Instruments 功能描述: